1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to forming electrical interconnects between circuit elements in semiconductor device areas of high transistor density.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a large number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a crystalline semiconductor layer. Due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require one or more additional “wiring” layers, which are sometimes referred to as metallization layers, or metallization systems. These metallization layers generally include substantially horizontally oriented conductive lines, which are typically formed of highly conductive metals and provide intra-level electrical connections—i.e., within the plane of a given metallization layer. Additionally, metallization layers may also include a plurality of substantially vertically oriented conductive connections, sometimes referred to as contact “vias,” that may also be filled with an appropriate highly conductive metal, and which provide inter-level electrical connections—i.e., between the planes of two neighboring stacked metallization layers.
In state-of-the-art semiconductor technologies, electrical connections, or interconnects, between the various circuit elements of a semiconductor device, such as transistors, capacitors, resistors, diodes, and the like, are typically established by connecting the circuit elements with the “wiring” components of the metallization layers. These interconnects are accomplished through a vertical contact structure, or contact layer, that is typically provided between the circuit elements formed in and above a semiconductor substrate and the metallization layers thereabove. The contact layer may include a plurality of vertical contact elements, such as contact vias, which connect the respective contact regions of a given circuit element—such as a gate electrode and/or the drain/source regions of a transistor element—to a respective metal line in the first metallization layer. Typically, the contact vias comprising the contact layer are formed in an interlayer dielectric material that encloses and passivates the circuit elements. FIG. 1 depicts one prior art method of providing electrical interconnects between illustrative transistor elements of a semiconductor device, and will now be described.
FIG. 1 schematically shows a cross-sectional view of an illustrative prior art semiconductor device 100 that includes a MOS transistor elements 150a-d in an advanced manufacturing stage, wherein a first metallization layer has already been formed. The semiconductor device 100 of FIG. 1 may also include a substrate 101, in and above which the illustrative transistor elements 150a-d may be formed based on well-established semiconductor device processing techniques. For example, the transistor elements 150a-d each may include a gate electrode structure 125, and the substrate 101 may represent any appropriate substrate which may contain or on which may be formed a semiconductor layer 103, such as a silicon-based layer, or any other appropriate semiconductor material that may facilitate the formation of the MOS transistor elements 150a-d. It should be appreciated that the semiconductor layer 103, even if provided as a silicon-based layer, may include other materials, such as germanium, carbon, and the like, in addition to an appropriate dopant species for establishing the requisite conductivity types in each of the active regions 102a-d of the semiconductor layer 103. Furthermore, in some illustrative embodiments, the transistor element 150 may be formed as one of a plurality of bulk transistors, i.e., the semiconductor layer 103 may be formed on or be part of a substantially crystalline substrate material, while in other cases specific device regions of the device 100 or the entire device 100 may be formed on the basis of a silicon-on-insulator (SOI) architecture, in which a buried insulating layer (not shown) may be provided below the semiconductor layer 103.
As shown in FIG. 1, the active regions 102a-d may typically be enclosed by an isolation structure 104, which in the present example may be provided in the form of a shallow trench isolation that is typically used for sophisticated integrated circuits. In the illustrated device, highly doped source regions 105 and drain regions 106, which in some cases may also include lightly doped extension regions, are formed in each of the active regions 102a-d, corresponding to each of the transistor elements 150a-d, respectively. The source and drain regions 105, 106, including any extension regions, are laterally separated by a channel region 107. Furthermore, the source and drain regions 105, 106 may also include, among other things, metal silicide contact regions (not shown), which may facilitate the formation of electrical contacts to one or more of the transistor elements 150a-d. Each of the gate electrode structures 125 are formed above the channel regions 107 of the respective transistor elements 150a-d, and include a gate electrode 109, which is separated from the underlying channel region 107 by a gate dielectric layer 108. Additionally, depending on the overall device requirements and the process flow used to form the transistor elements 150a-d, the gate electrode structures 125 may also include sidewall spacer structures 110 on or adjacent to the sidewalls of the gate electrode 109. Depending on the device requirements and/or the process strategy, a transistor may include one, two, or even more spacer elements, such as offset spacers, conformal liners, and the like, which may act as appropriate implantation masks for creating the lateral dopant profile for the highly doped drain and source regions 105, 106, as well as any lightly doped extension regions.
Depending on the specific requirements of the semiconductor device 100, the transistor elements 150a-d may be spaced at a gate electrode pitch 161 of less than 100 nm, and in certain applications may be even be spaced at 80 nm or less. Moreover, each of the transistor elements 150a-d may in some cases be substantially similar in design and configuration, whereas in other cases one or more of the transistor elements 150a-d may be of a substantially different design. For example, in some instances all of the transistor elements 150a-d may be of the same conductivity type, such as NMOS or PMOS transistors, and furthermore may all be formed based upon the same integration process. In other instances, the transistor elements 150a-d may be based upon CMOS device architecture, wherein pairs of transistor elements are made up of one each of an NMOS transistor and a PMOS transistor. Additionally, in some designs, one or more of the gate electrode structures 125 may be based upon conventional gate electrode configurations—sometimes referred to as “polySiON” configurations—wherein the gate electrode 109 is generally formed from polysilicon material, and the gate dielectric layer 108 is formed from an oxide, such as silicon dioxide, silicon oxynitride, and the like. On the other hand, in other designs, some of the gate electrode structures 125 may be based on more advanced materials, which may include high-k gate dielectric materials (i.e., materials having a dielectric constant “k” greater than approximately 10, such as hafnium oxide, tantalum oxide, titanium oxide, and the like) and highly conductive metal gate electrode materials (such as titanium, titanium nitride, titanium-aluminum, tantalum, and the like), which, in combination, is sometimes referred to as a high-k dielectric/metal gate stack, or “HK/MG” gate electrode configuration.
The semiconductor device 100 may also include an interlayer dielectric (ILD) material layer 111, sometimes also referred to as a contact dielectric layer 111, which typically serves to electrically isolate the transistor elements 150a-d from any subsequently formed metallization layers, such as the first metallization layer 119 shown in FIG. 1. The contact dielectric layer 111 may include one or more of several well-known conventional silicon-based dielectric materials, such silicon dioxide, silicon nitride, silicon oxynitride, and the like. Depending on the device design and overall process flow requirements, the contact dielectric layer 111 may also include suitably selected low-k dielectric materials, such as porous silicon dioxide, organic polyimides, or organosilicates such as methyl silsesquioxane (MSQ) and the like, wherein it should be understood that a low-k dielectric material may be considered as a material having a k-value that is approximately 3 or less.
In the illustrative semiconductor device 100 depicted in FIG. 1, the contact dielectric layer 111 includes a first conformal dielectric material layer 111a and a second dielectric material layer 111b. In certain cases, the first dielectric material layer 111a may act as an etch stop layer when forming contact elements—such as contact vias 117a-d shown in FIG. 1—to the various contact regions of each transistor element 150a-d, wherein the composition of the first dielectric material layer 111a is exhibits a substantially different etch rate as compared to the material of the second dielectric material layer 111b. For example, when the second dielectric material layer 111b makes up the bulk of the contact dielectric layer 111 and includes, for example, silicon dioxide, then the first dielectric material layer 111a may also include, for example, silicon nitride, which exhibits etch selectivity relative to silicon dioxide.
As noted, the semiconductor device 100 of FIG. 1 also includes a plurality of contact vias 117a-d, each of which form a substantially vertically oriented conductive path between the conductive lines 120a-d of the first metallization layer 119 and the gate electrodes 109 of each of the transistor elements 150a-d. Depending on specific device requirements, the contact vias 117a-d may include of one or more highly conductive metal materials, such as, for example, tungsten and the like. Furthermore, in some cases a liner or barrier layer (not shown) may be formed on the sidewalls of the via openings, between the contact vias 117a-d and the materials making up the contact dielectric layer 111, so as to promote contact element adhesion, and/or prevent material diffusion, as is well understood by those having ordinary skill in the art.
FIG. 1 also schematically depicts a first metallization layer 119 formed above the contact dielectric layer 111. An etch stop or hard mask layer (not shown) may also be present between contact dielectric layer 111 and the first metallization layer 119, which, depending on the device integration requirements, may be used to facilitate the planarization of the contact dielectric layer 111 after the contact vias 117a-d have been formed. The first metallization layer 119 may be formed of any one of several suitable dielectric materials well known in the art, such as silicon dioxide, silicon oxynitride, or even low-k dielectric materials. Furthermore, the first metallization layer 119 may include a plurality of substantially horizontally oriented “wiring” elements, such as the conductive lines 120a-d, which, depending on the overall circuit design, may be configured and routed through the first metallization layer 119 so as to provide electric connections between the various circuit elements making up the semiconductor device 100. In many integrated circuits based on advanced device integration schemes, the conductive lines 120a-d may include highly conductive metals, such as copper and copper alloys. As those skilled in the art know, the processing of wiring elements based on copper and copper alloys is typically based on the so-called damascene technique, wherein a series of sophisticated photolithography and etching steps are used to form openings in a dielectric material layer, which define the size and extent of a wiring circuit. Thereafter, the openings are filled using electrochemical deposition processes, such as electroplating and the like.
As noted above, the first metallization layer 119 may typically include a plurality of interconnects between a variety of integrated circuit elements. For example, as shown in FIG. 1, a conductive line 120a may be formed in the first metallization layer 119 so as to provide a direct electrical connection between the gate electrodes 109 of transistor elements 150a and 150b. This type of direct gate electrode-to-gate electrode connection is typical in certain semiconductor devices, such as, for example, a 6T (six transistor) static random-access memory (SRAM) chip, the circuit layout of which may require a direct connection between the gate electrode of a PMOS pull-up transistor and the gate electrode of an NMOS pull-down transistor. Therefore, in FIG. 1, the conductive line 120a may be representative of an electrical interconnect between the gate electrodes of a pair of transistor elements of a first inverter of a 6T SRAM memory cell, in which case, the transistor element 150a may represent, e.g., an NMOS pull-down transistor, and the transistor element 150b may represent, e.g., a PMOS pull-up transistor.
In addition to the conductive line 120a that provides a direct interconnect between the gate electrodes 109 of the transistor elements 150a and 150b, the first metallization layer 119 may also include a plurality of additional conductive lines, such as the conductive lines 120b, 120c and 120d, which may provide further electrical interconnects to other circuit elements of the semiconductor device 100. However, due to some device design and operating parameters, such as power requirements, current density, and the like, a minimum spacing 162 may need to be established between adjacent conductive lines so as to limit undue parasitic capacitance effects. Accordingly, depending on the overall circuit layer and conductive line density requirements, the minimum spacing 162 between adjacent conductive lines may have a substantial influence on the gate electrode pitch 161.
It should be appreciated that, in view of the continued and ongoing success within the semiconductor processing industry of reducing the physical size of semiconductor elements so as to increase device performance, and to fit more devices on a given chip area, inherent limitations on the spacing between adjacent conductive lines within a given metallization layer is becoming of increased importance. For example, as devices generally become smaller, the spacing between devices also becomes smaller, device density increases, and less real estate is available in a given metallization layer within which to route the requisite number electrical interconnects. In particular, in chip areas having a very high density of transistor elements, such as the aforementioned SRAM memory devices, and the like, the first metallization layer—wherein the connections to the various circuit elements is initially established—may also include a very high density of conductive lines. As the conductive lines become more closely spaced, the problems associated with parasitic capacitance between adjacent lines may become more pronounced, metal-to-metal leakage current may increase, and overall device degradation may occur. These factors may in turn have a significant effect on overall device performance and reliability.
Accordingly, there is a need to implement new design strategies to address the manufacturing and performance issues associated with electrical interconnects in areas of high semiconductor device density. The present disclosure relates to process schemes and devices that are directed to avoiding, or at least mitigating, the effects of one or more of the problems identified above.